1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method for manufacturing the LCD device to increase contact stability by increasing a contact area when a contact hole is formed on a surface of a metal layer using a diffraction mask.
2. Discussion of the Related Art
As information society develops, the demand for various displays increases. Recently, many efforts have been made to research and develop various flat display panels such as LCDs (liquid crystal displays), PDPs (plasma display panels), ELDs (electroluminescent displays), VFDs (vacuum fluorescent displays), and the like. And, some species of the flat display panels are already applied to the displays of various equipments.
LCD is widely used because of the characteristics or advantages of high quality image, lightness, thin & compact size, and low power consumption. Thus, it is used as a substitution for a CRT (cathode ray tube) as a mobile image display. The LCD is also developed to be applicable to devices receiving broadcasting signals, such as televisions, computer monitors, and the like.
Even if various technical developments of LCD have been made to play a role as an image display in various fields, the image quality for an image display fails to meet the characteristics and advantages of LCD.
In order to apply a liquid crystal display device as a general display device to various fields, the development of LCD depends on realizing a high quality image of high resolution, high brightness, wide screen, and the like as well as maintaining the characteristics of lightness, thin compactness, and low power consumption.
A general liquid crystal display includes two substrates having an electric field generating electrodes formed thereon respectively to confront each other, and liquid crystals injected between the two confronting substrates. If a voltage is applied to the electrodes to generate an electric field, liquid crystals molecules are driven to display an image in accordance with the light transmittance varied by the electric field.
There are various types of the liquid crystal displays. And, great attention is paid to an active matrix liquid crystal display (AM-LCD) on which thin film transistors and pixel electrodes connected to each other are arranged by a matrix system to provide excellent resolution and implementation of moving pictures.
Such a liquid crystal display has a structure where pixel and common electrodes are formed on lower and upper substrates, respectively, and drives liquid crystal molecules by applying an electric field between the substrates in a direction vertical to the substrates.
A liquid crystal display according to a related art is explained by referring to the attached drawings as follows.
Referring to FIG. 1, a plurality of gate lines 11 are formed in one direction on a lower array substrate 10 of a liquid crystal display, and a gate electrode 12 protruding from one side of each of the gate lines 11 is formed. A gate pad 11a is formed at one end of each gate line 11 with a predetermined area. A gate insulating layer 22 (shown in FIG. 2) is formed on an entire surface of the lower array substrate 10 including the gate lines 11, the gate electrodes 12 and the gate pad 11a. 
A plurality of data lines 14 are formed perpendicular to the gate lines 11, and cross the gate lines 11 to define pixel areas, respectively. A source electrode protrudes from one side of each of the data lines 14, and a drain electrode 16 is separated from the source electrode 15 to leave a predetermined interval. A data pad 14b having a contact hole 17c is formed at one end of each data line 14 with a predetermined area.
Moreover, the source, drain, and gate electrodes 15, 16, and 12 construct a thin film transistor T including an active layer of amorphous silicon over the gate electrode 12.
The source and drain electrodes 15 and 16 are overlapped with both upper sides of the gate electrode 12.
A pixel electrode 18 made of a transparent conductive material is formed on each of the pixel areas to be overlapped with the drain electrode 16 in part, and a contact hole 17 is formed at the portion where the pixel and drain electrodes 18 and 16 are overlapped with each other.
Meanwhile, a storage capacitor Cst is formed to maintain a cell voltage.
In this case, an upper electrode of the storage capacitor Cst is made of an opaque metal layer 14a having a predetermined pattern and a lower electrode of the storage capacitor Cst is made of the gate line 11 on a front end.
The opaque metal layer 14a is overlapped with the gate line 11 on the front end in part when the data line 14 is formed, and is overlapped with the pixel electrode 18 in part as well.
And, a contact hole 17a exposing a predetermined portion of the opaque metal layer 14a is formed together with the contact hole 17. Hence, the gate line 11, the opaque metal layer 14a, and an insulating layer inserted between the gate line 11 and opaque metal layer 14a, construct the storage capacitor Cst when a voltage is applied to the pixel electrode 18. During the formation of the contact holes 17 and 17a, a process step for exposing a portion of the gate pad 11a is performed with a process step for etching a passivation layer 24 and a gate insulating layer 22.
A storage-on-gate system is shown in the drawing, and has the structure where the lower electrode of the storage capacitor is built in one body with the gate line on the front end.
A cross-sectional view of such an array substrate is shown in FIG. 2 illustrating a cross-sectional view along cutting lines V-V′ and VI-VI′ in FIG. 1, in which a storage electrode part A, a thin film transistor (TFT) part B and a gate pad part C are separated from one another for explanation. The same elements are indicated by the same reference numerals.
Referring to FIG. 2, a gate line 11 is formed in the storage electrode part A on a lower array substrate 10 and a gate electrode 12 extending from the gate line 11 is formed in the thin film transistor part B. A gate insulating layer 22 is formed on an entire surface of the storage electrode and thin film transistor parts A and B.
An active layer 13 is formed in a thin film transistor forming area on the gate insulating layer 22 of the thin film transistor part B. The active layer 13 includes an amorphous silicon layer 13a and a doped semiconductor layer 13b formed on the amorphous silicon layer 13a for ohmic contact and etch prevention.
Source and drain electrodes 15 and 16 are arranged to overlap with both side ends of the doped semiconductor layer 13b, respectively. In this case, the source electrode 15 is an electrode extending from the data line 14, and the drain electrode 16 is spaced apart from the source electrode 15.
An opaque metal layer 14a overlapped with the gate line 11 is formed in the storage electrode part A simultaneously when the source and drain electrodes 15 and 16 are formed. The gate pad 11a is formed in the gate pad part C, and the gate insulating layer 22 is formed on the lower array substrate 10 including the gate pad 11a. 
A passivation layer 24 is formed on the entire surface of the lower array substrate 10 having the opaque metal layer 14a, source and drain electrodes 15 and 16 and gate pad 11a. 
Contact holes 17, 17a and 17b exposing predetermined portions of the drain electrode 16, the opaque metal layer 14a, and the gate pad 11a are respectively formed in the passivation layer 24. And, a pixel electrode 18 made of a transparent material is formed on the passivation layer 24 in the pixel area so as to be in contact with the drain electrode 16 and the opaque metal layer 14a. A transparent material 18a is also formed in the hole 17b to be in contact with the gate pad 11a. 
In the fabrication of the above-constituted liquid crystal display device, the metal layer for the source and drain electrodes 15 and 16 includes Mo instead of Cr.
FIG. 3 illustrates a cross-sectional view of a liquid crystal display device to which a storage-on-gate system is applied using Mo as the source and drain electrodes 15 and 16.
Referring to FIG. 3, in the process of forming the contact holes 17 and 17a by dry-etching the passivation layer 24 and thereby exposing upper portions of the opaque metal layer 14a and the drain electrode 16 after the passivation layer 24 has been formed, Mo fails to have etch selectivity with the etchant gas of the passivation layer 24. Hence, the opaque metal layer 14a and drain electrode 16 made of Mo may be etched since the gate pad 11a being formed at one end of the gate line 11 is exposed during the formation of the contact holes 17 and 17a. That is, since it is required to etch the gate insulating layer 22 as well as the passivation layer 24 in order to expose the gate pad 11a, the opaque metal layer 14a and the drain electrode 16 are also simultaneously etched because the opaque metal layer 14a and the drain electrode 16 are made of Mo having low etch selectivity and are exposed during the formation of the contact holes 17 and 17a. 
If portions of the opaque metal layer 14a and drain electrode 16 are etched away when the contact holes 17 and 17a are formed, the pixel electrode 18 would likely come into contact with only the exposed lateral sides of the opaque metal layer 14a and drain electrode 16 as shown in the dotted circles of FIG. 3.
Thus, if a contact area of the opaque metal layer 14a and/or drain electrode 16, which is contacted with the pixel electrode 18, decreases as shown in FIG. 3, a contact resistance of the LCD device increases which in turn causes PDs (point defects) in the LCD devices.